The present invention generally relates to an integrated circuit having an output circuit, and more particularly to an integrated circuit having an output circuit which is coupled to a bus or a transmission line.
Recently, there has been considerable activity in the development of a system such as a local area network in which a plurality of bus receivers and bus transmitters hold a bidirectional bus in common. In such a system, it is desired that data is exchanged at high speeds between the bidirectional bus and the bus receivers or transmitters. Further, the bus receivers or bus transmitters must be protected from an overvoltage (between a recommended operation voltage and a maximum rated voltage) applied thereto through the bidirectional bus.
FIG. 1 is a circuit diagram of a conventional output circuit which serves as a bus transmitter. Referring to FIG. 1, an output circuit 1 is made up of transistors Q1-Q5, a diode (Schottky diode) D1, and resistors R1 and R2. Each of the transistors Q1, Q3 and Q4 includes a Schottky diode. The transistors Q1 and Q2 and the diode D1 form a first switching circuit 2. A second switching circuit 3 includes the transistor Q3. A binary logic signal S1 supplied from an input circuit or an internal circuit (not shown) of a device related to the output circuit 1 is applied to the base of the transistor Q4. In response to the binary logic signal S1, the transistor Q4 turns ON either the first switching circuit 2 or the second switching circuit 3. When the first switching circuit 2 is turned ON, the level of an output terminal X is set approximately equal to a power source voltage Vcc. On the other hand, when the second switching circuit 3 is turned ON, the level of the output terminal X is set approximately equal to a ground potential (GND). The resistor R1 generates a voltage proportional to an emitter current passing through the transistor Q3. The generated voltage is applied to the base of the transistor Q5 and causes the base voltage of the transistor Q5 to increase. Accordingly, the emitter current of the transistor Q3 decreases as an increase of the base voltage of the transistor Q5.
That is, when the binary logic signal S1 is switched to logic "0", the transistor Q4 turns OFF, and the transistors Q1 and Q2 of the first switching circuit 2 turn ON. Thereby, the logic of the output terminal X is set to logic "1" (equal to Vcc - 2V.sub.BE). On the other hand, when the binary logic signal S1 is switched to logic "1", the transistor Q4 turns ON and the transistor Q3 of the second switching circuit 3 turns ON. Thereby, the logic of the output terminal X is set to logic "0" (approximately equal to the ground potential). When an overvoltage is applied to the output terminal X with the transistor Q3 ON, the transistor Q5 suppresses the emitter current of the transistor Q3 so that the transistor Q3 can be prevented from being broken down.
The resisting voltage of the output circuit 1 viewed from the output terminal X is based on characteristics of the transistors Q1-Q5. Particularly, the resisting voltage of the output circuit is mainly based on the reverse emitter-base breakdown voltage BV.sub.EBO of each of the transistors Q1 and Q2 when the logic of the output terminal X is "0". For this reason, the conventional output circuit does not satisfy the maximum rating defined by a standard such as RS485 in the EIA (Electronic Industries Association) standard.
The above-mentioned RS485 standard is frequently applied to a bus receiver and a bus transmitter which hold a bidirectional bus in common. The recommended operating condition of the RS485 standard is equal to or less than 12 volts. The maximum rating which is generally applied to integrated circuits in conformity with the RS485 standard is equal to or less than 15 volts.
Output resisting (breakdown) voltages BV.sub.OH and BV.sub.OL for logics H and L are described by the following formulas (1) and (2), respectively: ##EQU1## where V.sub.BE5 is the forward base-emitter voltage of the transistor Q5, V.sub.BE3 is the forward base-emitter voltage of the transistor Q3, V.sub.CE4 is the forward collector-emitter saturation voltage of the transistor Q4, the BV.sub.EB01 is the reverse emitter-base breakdown voltage of the transistor Q1, and BV.sub.EB02 is the reverse emitter-base breakdown voltage of the transistor Q2.
The output resisting voltage BV.sub.OH equal to 16 volts sufficiently satisfies the maximum rating equal to 15 volts. On the other hand, the output resisting voltage BV.sub.OL equal to 13 volts does not satisfy the maximum rating. Therefore, when an overvoltage in excess of the recommended operating condition under the maximum rating is applied to the output terminal X from the outside of the output circuit 1 in the state where the output logic of the output circuit 1 is "0", the transistors Q1 and Q2 may be broken down. In order to get rid of this possibility, it is conceivable to deep base diffusion for the transistors Q1 and Q2 so that the voltages BV.sub.EB01 and BV.sub.EB02 can be increased so as to satisfy the RS485 standard. However, such an idea presents another disadvantage in that signal transmission becomes slow as the base diffusion is deepened.